xilinx的FPGA xc2v2000有16个时钟管脚

65M
最好看看应用实例，
时钟分全局时钟gclk和rhclk,lhclk
下面为英文解读
Either a user-I/O pin or Input-only pin, or an input to a specific clock buffer
driver. Every package has 16 global clock inputs that optionally clock the
entire device. The RHCLK inputs optionally clock the right-half of the
device. The LHCLK inputs optionally clock the left-half of the device. Some
of the clock pins are shared with the dual-purpose configuration pins and
are considered DUAL-type. See the Clocking Infrastructure section in
Module 2 for additional information on these signals.
IO_Lxxy_#/GCLK[15:10, 7:2]
IP_Lxxy_#/GCLK[9:8, 1:0]
IO_Lxxy_#/LHCLK[7:0]
IO_Lxxy_#/RHCLK[7:0]

CLK period 不是应该属于UCF里的东西么。 你要求多少频率的时钟就接多少。但是时钟太高 UCF 报错 就 降频率或者 改设计吧