求：VHDL verilog 互相调用的例子，要能综合的例子，不要在网上随便复制过来一个例子。高分感谢~~

VHD调用verilog：
module sync_block #(
parameter INITIALISE = 2'b00
)
(
input clk, // clock to be sync'ed to
input data_in, // Data to be 'synced'
output data_out // synced data
);
//VHD
entity dcm_reset is
port(
ref_reset : in std_logic; -- Synchronous reset in ref_clk domain
ref_clk : in std_logic; -- Reliable reference clock of known frequency (125MHz)
dcm_locked : in std_logic; -- The DCM locked signal
dcm_reset : out std_logic -- The reset signal which should be connected to the DCM
);
end dcm_reset;
component sync_block
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
end component;
dcm_locked_sync_tx : sync_block
port map(
clk => ref_clk,
data_in => dcm_locked,
data_out => dcm_locked_sync
);
verilog调用VHD：（目标还是上述VHD模块）
module gmii_if (
……
）;
dcm_reset rx_dcm_reset (
.ref_reset (tx_reset),
.ref_clk (tx_clk),
.dcm_locked (dcm_locked),
.dcm_reset (reset_200ms)
);