vhdl 8选1数据选择器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY EIGHT_XUAN_1 IS
PORT( ST: IN STD_LOGIC;
A: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
D: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Q: OUT STD_LOGIC);
END;
ARCHITECTURE HBV OF EIGHT_XUAN_1 IS
SIGNAL Q1: STD_LOGIC;
BEGIN
PROCESS(A)
BEGIN
IF ST='1' THEN Q1<='0';
ELSE
CASE A IS
WHEN "000"=> Q1 <= D(0);
WHEN "001"=> Q1 <= D(1);
WHEN "010"=> Q1 <= D(2);
WHEN "011"=> Q1 <= D(3);
WHEN "100"=> Q1 <= D(4);
WHEN "101"=> Q1 <= D(5);
WHEN "110"=> Q1 <= D(6);
WHEN "111"=> Q1 <= D(7);
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
Q<= Q1;
END HBV;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mux81 IS
PORT(
X:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
A,B,C,D,E,F,G,H:IN STD_LOGIC;
Y:OUT STD_LOGIC
);
END MUX81;
ARCHITECTURE O OF MUX81 IS
BEGIN
Y<=A WHEN X="000" ELSE
B WHEN X="001" ELSE
C WHEN X="010" ELSE
D WHEN X="011" ELSE
E WHEN X="100" ELSE
F WHEN X="101" ELSE
G WHEN X="110" ELSE
H WHEN X="111" ;
END O;